1. Field of the Invention
The present invention relates generally to high voltage metal-oxide semiconductor (MOS) transistors and more specifically to improvements that lower the inherent on-resistance of high voltage MOS transistors.
2. Description of the Prior Art
Insulated gate field effect transistors (IGFETs) or MOSFETs are conventionally placed in series with junction field effect transistors (JFETs) to make combination devices that can switch high voltages and that have low values of on-resistance. A lightly doped extended drain region is used so that the voltage is sustained by an offset gate. The voltage capability of such devices is determined by the doping of the substrate, the length of the extended drain region and the net number of charges therein. Improvement in on-resistance is substantially limited by the cross sectional area, length and degree of doping in the extended drain region.
U.S. Pat. No. 4,811,075, issued Mar. 7, 1989 to the present inventor, Klas H. Eklund, describes an insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity material. A top layer of material similar to the substrate is formed by ion implantation. The top layer covers a middle part of the extended drain. Current flow through the extended drain is controlled by the substrate and top layer which pinch-off the extended drain between them in a familiar field-effect fashion.
The extended drain region requires high levels of doping to achieve acceptable levels of conductivity. The resistance of the device when it is switched on will be very much dependent on the dimensions of the extended drain region and its doping concentration. Generally, those adjustments in these parameters that improve on-resistance will degrade voltage handling capability, and vice versa.
A lateral double-diffused MOS transistor device for source follower applications is described in U.S. Pat. No. 4,626,879, issued Dec. 2, 1986, to Sel Colak. An intermediate semiconductor layer of the same conductivity type as the channel region extends laterally from the channel region to beneath the drain contact region of a device. Colak states that this intermediate semiconductor layer substantially improves the punch through and avalanche breakdown characteristics of the device, thus permitting operation in the source-follower mode. A compact structure which features a relatively low normalized "`on` resistance" is also claimed. However, the on-resistance is not as low as it could be. FIG. 1 in Colak reveals that intermediate layer 16 isolates layer 18 from layer 14. Channel currents do not have the opportunity to flow both over and under the intermediate layer 16. In the present invention, the equivalent of the intermediate layer stops short, and thus permits dual current paths and concomitant lower on-resistance values.
An improved high voltage MOS transistor is needed in which very low levels of on-resistance can be realized without sacrificing high voltage performance.